The present invention relates generally to power systems, and, more particularly, to a design structure for indicating status of an on-chip power supply system.
On-chip power systems for integrated circuits have become increasingly popular as they eliminate the need for providing several different voltage levels from external sources. It is common to have several power systems serving several memory sub-systems.
As one example, in a chip including memory macros, such as an embedded dynamic random memory (eDRAM) chip, it is necessary to provide many different voltage levels to effectively achieve performance. For example, there needs to be one voltage level (VPP) to provide a voltage greater than supply voltage Vdd, for a boosted wordline operation to enhance cell signal and access time. A negative voltage, (VBB), is needed to bias the body of the transfer devices in the memory array so that sub-threshold leakage of the cell is minimized. In some memory chip designs there may also be an additional negative voltage (VWL) to hold unselected wordlines to a level below ground so that the sub-threshold leakage of the array devices can be suppressed to improve cell retention. Additionally, a bandgap reference voltage (VBGR) is needed to provide a constant and stable reference voltage insensitive to variations in the supply voltage Vdd, and temperature. Another voltage reference (VREFDC), which varies with the supply voltage, is needed to generate voltage levels which are designed to track the supply voltage. Another bandgap circuit output is constant current reference (VCMN), which may be used to bias differential amplifiers, etc.
Diagnostics become difficult in an Application Specific Integrated Circuit (ASIC) chip having several power systems serving several memory sub-systems because the power system voltages are not observable at test. Internal probing of a failed chip is not practical under several metal levels, and consequently, field failures are presently very difficult to diagnose.
Thus, there exists a need for a technique for simply and effectively diagnosing failures in on-chip power supply systems.